The present invention relates to packetized dynamic random access memory devices, and more particularly, to a method in apparatus for detecting a signal indicating the start of an initialization procedure that adjusts the timing of an internal clock signal used to strobe the initialization signal and a command packet.
Conventional computer systems include a processor (not shown) coupled to a variety of memory devices, including read-only memories (xe2x80x9cROMsxe2x80x9d) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (xe2x80x9cSRAMxe2x80x9d). The processor also communicates with input devices, output devices, and data storage devices.
Processors generally operate at a relatively high speed. Processors such as the Pentium(copyright) and Pentium II(copyright) microprocessors are currently available that operate at clock speeds of at least 400 MHz. However, the remaining components of the computer system, with the exception of SRAM cache memory, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a frequency that is substantially lower than the clock frequency of the processor. Currently, for example, a processor having a 200 MHz clock frequency may be mounted on a mother board having a 66 MHz clock frequency for controlling the system memory devices and other components.
Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 200 MHz, to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.
System memory devices are generally dynamic random access memories (xe2x80x9cDRAMsxe2x80x9d). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs, which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (xe2x80x9cSDRAMsxe2x80x9d) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are typically incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.
A solution to this operating speed disparity has been proposed in the form of a computer architecture known as xe2x80x9cSyncLink.xe2x80x9d In the SyncLink architecture, the system memory may be coupled to the processor, either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, SyncLink memory devices receive command packets that include both control and address information. The SyncLink memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus.
An example of a computer system 10 using the SyncLink architecture is shown in FIG. 1. The computer system 10 includes a processor 12 having a processor bus 14 coupled to three packetized dynamic random access memory or SyncLink DRAM (xe2x80x9cSLDRAMxe2x80x9d) devices 16a-c through a memory controller 18. The computer system 10 also includes one or more input devices 20, such as a keypad or a mouse, coupled to the processor 12 through the processor bus 14, a bus bridge 22, and an expansion bus 24, such as an Industry Standard Architecture (xe2x80x9cISAxe2x80x9d) bus or a Peripheral Component Interconnect (xe2x80x9cPCIxe2x80x9d) bus. The input devices 20 allow an operator or an electronic device to input data to the computer system 10. One or more output devices 30 are coupled to the processor 12 to display or otherwise output data generated by the processor 12. The output devices 30 are coupled to the processor 12 through the expansion bus 24, bus bridge 22 and processor bus 14. Examples of output devices 24 include printers and a video display units. One or more data storage devices 38 are coupled to the processor 12 through the processor bus 14, bus bridge 22, and expansion bus 24 to store data in or retrieve data from storage media (not shown). Examples of storage devices 38 and storage media include fixed disk drives floppy disk drives, tape cassettes and compact-disk read-only memory drives.
In operation, the processor 12 communicates with the memory devices 16a-c via the memory controller 18. The memory controller 18 sends the memory devices 16a-c command packets that contain both control and address information. Data is coupled between the processor 12 and the memory devices 16a-c through the memory controller 18 and the processor bus 14. Although all the memory devices 16a-c are coupled to the same conductors of the memory controller 18, only one memory device 16a-c at a time reads or writes data, thus avoiding bus contention. Bus contention is avoided by each of the memory devices 16a-c having a unique identifier, and the command packet containing an identifying code that selects only one of these components.
The computer system 10 also includes a number of other components and signal lines that have been omitted from FIG. 1 in the interests of brevity. For example, as explained below, the memory devices 16a-c also receive a command clock signal to provide internal timing signals, a data clock signal clocking data into the memory device 16, and a FLAG signal signifying the start of a command packet.
One of the memory devices 16a is shown in block diagram form in FIG. 2. The memory device 16a includes a clock generator circuit 40 that receives a command clock signal CMDCLK and generates an internal clock signal ICLK and a large number of other clock and timing signals to control the timing of various operations in the memory device 16. The memory device 16 also includes a command buffer 46 and an address capture circuit 48, which receive the internal clock signal ICLK, a command packet CA0-CA9 on a 10-bit command bus 50, and a FLAG signal on line 52. The memory controller (not shown) or other device normally transmits the command packet CA0-CA9 to the memory device 16a in synchronism with the command clock signal CMDCLK. As explained above, the command packet, which generally includes four 10-bit packet words, contains control and address information for each memory transfer. The FLAG signal identifies the start of a command packet, and it also signals the start of an initialization sequence, as described in greater detail below. The command buffer 46 receives the command packet from the bus 50, and compares at least a portion of the command packet to identifying data from an ID register 56 to determine if the command packet is directed to the memory device 16a or some other memory device 16b, c. If the command buffer 46 determines that the command packet is directed to the memory device 16a, it then provides the command words to a command decoder and sequencer 60. The command decoder and sequencer 60 generates a large number of internal control signals to control the operation of the memory device 16a during a memory transfer.
The address capture circuit 48 also receives the command words from the command bus 50 and outputs a 20-bit address corresponding to the address information in the command packet. The address is provided to an address sequencer 64, which generates a corresponding 3-bit bank address on bus 66, a 10-bit row address on bus 68, and a 7-bit column address on bus 70. The column address and row address are processed by column and row address paths 73, 75 as will be described below.
One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The packetized DRAM 16a shown in FIG. 2 largely avoids this problem by using a plurality of memory banks 80, in this case eight memory banks 80a-h. After a memory read from one bank 80a, the bank 80a can be precharged while the remaining banks 80b-h are being accessed. Each of the memory banks 80a-h receive a row address from a respective row latch/decoder/driver 82a-h. All of the row latch/decoder/drivers 82a-h receive the same row address from a predecoder 84 which, in turn, receives a row address from either a row address register 86, redundant row circuit 87, or a refresh counter 88, as determined by a multiplexer 90. However, only one of the row latch/decoder/drivers 82a-h is active at any one time, as determined by bank control logic 94 as a function of a bank address from a bank address register 96.
The column address on bus 70 is applied to a column latch/decoder 100, which supplies I/O gating signals to an I/O gating circuit 102. The I/O gating circuit 102 interfaces with columns of the memory banks 80a-h through sense amplifiers 104. Data is coupled to or from the memory banks 80a-h through the sense amplifiers 104 and the I/O gating circuit 102 and a data path subsystem 108, which includes a read data path 110 and a write data path 112. The read data path 110 includes a read latch 120 that stores data from the I/O gating circuit 102. In the memory device 16a shown in FIG. 2, 64 bits of data are stored in the read latch 120. The read latch then provides four 16-bit data words to an output multiplexer 122 that sequentially supplies each of the 16-bit data words to a read FIFO buffer 124. Successive 16-bit data words are clocked into the read FIFO buffer 124 by a clock signal RCLK generated by the clock generator 40. The 16-bit words are then clocked out of the read FIFO buffer 124 by a clock signal obtained by coupling the RCLK signal through a programmable delay circuit 126. The read FIFO buffer 124 sequentially applies the 16-bit words to a driver circuit 128 in synchronism with the delayed RCLK signal. The driver circuit, in turn, applies the 16-bit data words to a data bus 130. The driver circuit 128 also applies the delayed RCLK signal to a clock line 132 as the DCLK signal. The programmable delay circuit 126 is programmed during initialization of the memory device so that the read data as received by the controller (not shown) processor, or other device has the optimum phase relative to DCLK signal at the controller, processor or other device for the DCLK signal to clock the read data into the memory controller (not shown), processor, or other device.
The write data path 112 includes a receiver buffer 140 coupled to the data bus 130. The receiver buffer 140 sequentially applies 16-bit words from the data bus 130 to four input registers 142, each of which is selectively enabled by a signal from a clock generator circuit 144. The clock generator circuit generates these enable signals responsive to the data clock DCLK, which, for write operations, is applied to the memory device 16a on line 132 from the memory controller, processor, or other device. As with the command clock signal CMDCLK and command packet CA0-CA9, the memory controller or other device (not shown) normally transmits the data to the memory device 16a in synchronism with the data clock signal DCLK. The clock generator 144 is programmed during initialization to adjust the timing of the clock signal applied to the input register 142 relative to the DCLK signal so that the input registers can capture the write data at the proper times. Thus, the input registers 142 sequentially store four 16-bit data words and combine them into one 64-bit data word applied to a write FIFO buffer 148. The data are clocked into the write FIFO buffer 148 by a clock signal from the clock generator 144, and the data are clocked out of the write FIFO buffer 148 by an internal write clock WCLK signal. The WCLK signal is generated by the clock generator 40. The 64-bit write data are applied to a write latch and driver 150. The write latch and driver 150 applies the 64-bit write data to one of the memory banks 80a-h through the I/O gating circuit 102 and the sense amplifiers 104.
Portions of the command buffer 46 is illustrated in greater detail in FIG. 3. With reference to FIG. 3, a command packet CA consisting of a plurality of packet words is applied to a shift register 202 via the command bus 50. The width of the bus 204 corresponds to the width of the shift register 202, and the number of packet words in the command packet corresponds to the number of stages of the shift register 202. In the embodiment shown in FIG. 3, the shift register 202 has four stages, each of which is 10 bits wide. Thus, the shift register 202 sequentially receives four 10-bit packet words CA less than 0:9 greater than . Each of the four packet words is shifted into the shift register 202, and from one shift register stage to the next, responsive to each transition of the internal clock signal ICLK.
Coincident with the start of each command packet during normal operation of the memory device 16a, the FLAG signal transitions high for one-half of the period of the internal clock signal ICLK. The flag signal FLAG, which is coupled to the memory device 16a via the flag line 52, is also applied to the shift register 202. In normal operation, the high FLAG signal is shifted through each of the four stages of the shift register 202 responsive to each transition of the ICLK signal. As a result, the F less than 0 greater than  bit of the shift register 202 transitions high on the transition of the ICLK signal following the FLAG signal transitioning high. On the next transition of the ICLK signal, the F less than 0 greater than  bit transitions low and the F less than 1 greater than  bit transitions high, on the next transition of the ICLK signal the F less than 1 greater than  bit transitions low and the F less than 2 greater than  bit transitions high, etc. Thus, in normal operation, only one F less than 3:0 greater than  bit is high at a time.
When four packet words have been shifted into the shift register 202, an F less than 3 greater than  signal is generated at the output of the shift register 202. The F less than 3 greater than  signal then loads the 40 bit contents of the shift register 202 into a storage register 208. In the embodiment shown in FIG. 3 in which four 10-bit packet words are shifted into the shift register 202, the storage register 208 receives and stores a 40-bit command word in addition to shifting the FLAG signal through the shift register 202. However, in the more general case, the shift register 202 has N+1 stages, each of which has a width of M bits, and the storage register 208 loads an M*N bit command word. After the storage register 208 has been loaded, it continuously outputs the M*N bit command word Y less than 39:0 greater than .
As further shown in FIG. 3, the internal clock signal ICLK is generated from the command clock signal CMDCLK by the clock generator 40. The phase of the internal clock signal ICLK relative to the phase of the command clock signal CMDCLK controlled by and the phases of the DCLK and WCLK signals are controlled by respective values of PHASE bits, which are generated by a logic circuit (not shown in FIG. 3). The values of PHASE are determined during initialization, as described above and in greater detail in U.S. patent application Ser. No. 08/890,055 to Baker et al., which is incorporated herein by reference.
It will be understood that necessary portions of the command buffer and clock generator circuit 200 have been omitted from FIG. 3 in the interests of brevity since they are somewhat peripheral to the claimed invention. For example, the command buffer 48 will contain circuitry for allowing the command buffer to determine if a command packet is directed to it, circuitry for pipelining command words output from the storage register 208, circuitry for generating lower level command signals from the command word, etc.
The relevant portions of the clock generator circuit 40 and the command buffer 46 are shown in greater detail in the block diagram of FIG. 4. As shown in FIG. 4, a timing control circuit 206 includes a clock circuit 220 that receives a clock signal CLK and its quadrature CLK90 from a conventional quadrature circuit 222 responsive to the internal clock signal ICLK. The internal clock signal ICLK is generated by the clock control circuit 40 from the command clock signal CMDCLK, as explained above with reference to FIG. 3. The CLK and CLK90 signals are applied to a NOR gate 232, which outputs a high whenever ICLK and ICLK90 are both low. The output of the NOR gate 232 is applied through a first inverter 234 to generate a CLK1 signal and then through a second inverter 236 to generate a CLK1* signal (the xe2x80x9c*xe2x80x9d symbol after a signal name is used throughout to designate the compliment of the signal).
The CLK90 and CLK signals are also applied to a NAND gate 240. which outputs a low whenever both CLK and CLK90 are high. The output of the NAND gate 240 is coupled through an inverter 242 to generate a CLK0 signal and then through a second inverter 244 to generate a CLK0* signal. These CLK0, CLK0*, CLK1, and CLK1* signals correspond to the ICLK signal described with reference to FIG. 3.
The clock generator circuit 40 also includes a pair of shift register circuits 246, 248 that are part of the shift register 202. The shift register circuits 246, 248 are connected in series with each other to form an 8-stage shift register. The shift register circuit 246 receives the FLAG signal, and the FLAG signal is then sequentially shifted through the four stages of the shift register circuit 246 and the four stages of the shift register circuit 248 responsive to the CLK0, CLK0*, CLK1, and CLK1* signals. As mentioned above, the FLAG signal is shifted through two stages of the shift register circuits 246, 248 each cycle of the CLK signals. Thus, when FLAG goes high, two successive F less than 0:7 greater than  outputs of the shift register circuits 246, 248 sequentially go high each clock cycle.
The shift register 202 shown in FIG. 4 also includes ten separate shift register circuits 250a-j, each of which receives a respective bit CA0-CA9 of the incoming 10-bit packet word coupled through respective buffers 251a-j. Each of the shift register circuits 250a-j includes four shift register stages. Thus, after four clock cycles, four packet word bits CA have been shifted into each shift register circuit 250, and all four of these bits are available as a 4-bit word B less than 0:3 greater than . Thus, the ten shift register circuits 250a-j collectively store and then output the 40-bit command word C less than 0:39 greater than .
The storage register 208 also receives the CLK and CLK 90 signals. However, bits B less than 0:3 greater than  for the four packet words stored in the shift register 202 are not latched into the storage register 208 until the F less than 3 greater than  signal is generated, as explained above. The F less than 3 greater than  signal is generated four transitions of the CLK signal after receipt of the FLAG signal, i.e., after four command packets have been shifted into the shift register 202. The storage register then stores and continuously outputs the 40-bit command word Y less than 0:39 greater than . The command word Y less than 0:39 greater than  is used to control the operation of a memory device containing the command buffer 46 and clock generator circuit 40.
The structure and operation of the command buffer 46 are described in greater detail in U.S. patent application Ser. No. 08/994,461 to Manning, which is incorporated herein by reference.
It is important that the clock signals generated from the ICLK signal be applied to the shift registers 250a-j at the proper time so that packet words CA0-9 on the command bus 50 are latched when valid packet words are present on the command bus 50. Similarly, it is important that the clock signals generated from the ICLK signal be applied to the shift registers 246, 248 at the proper time so that the FLAG signal on the flag line 52 are latched when a valid FLAG signal is present on the flag line 52. If the ICLK signal does not latch the FLAG signal at the proper time, the memory device 16a will fail to recognize the start of a command packet or it may fail to do so at the proper time. At higher operating speeds, it can become very difficult to ensure that the ICLK signal has the proper timing to accurately latch the command packet and the FLAG signal.
Even if the timing at which the CMDCLK signal, the command packet CA, and the FLAG signal are applied to the memory device 16a could be precisely controlled, it would be difficult to precisely control or predict the propagation delay of these signals within the memory device 16a. For example, internal signals require time to propagate to various circuitry in the memory device 16a. Differences in the signal path lengths can cause differences in the times at which signals reach the circuitry. Differences in capacitive loading of signal lines can also cause differences in the times at which signals reach the circuitry. These differences in arrival times can become significant at high operating speeds, and eventually limit the operating speed of memory devices.
The difficulty in clocking the packet words CA0-9 and the FLAG signal into the shift registers at the proper time can be explained with reference to FIG. 5. A bit of a command packet or the FLAG signal is shown in the upper portion of FIG. 5 having a leading edge occurring at t1 and a trailing edge occurring at t5. The internal clock signal is shown having a rising edge occurring at t3, which is midway between t1 and t5. However, as explained above, a variety of factors can alter the relative timing of the packet words and the FLAG signal relative to the ICLK signal as those signals are coupled to the memory device 16a and propagate through the memory device 16a to the shift register 202. As a result, the packet words CA0-9 and the FLAG signal may have a phase relative to each other that varies considerably. The packet word CA0-9 and the FLAG signal may be applied to the shift registered 202 at a time relative to the ICLK signal starting at t0, in which case it would terminate at time t2. The packet word CA0-9 and the FLAG signal may also be applied to the shift registered 202 at a time relative to the ICLK signal starting at t4, in which case it would terminate after time t5. Under these circumstances, the transition of the ICLK must occur during the shaded portion of the packet word CA0-9 and FLAG signal between t2 and t4. It can therefore be seen that there is very little tolerance in the phase of the ICLK signal relative to the phases of the packet word CA0-9 and the FLAG signal.
The command buffer 46 illustrated in FIGS. 3 and 4 is able to precisely control the timing of the ICLK signal because the clock control circuit 40 adaptively adjusts the phase of the ICLK signal relative to the CMDCLK signal so that the shift register 202 is clocked at the proper time. As explained in greater in the above-cited U.S. patent application Ser. No. 08/890,055 to Baker et al., during initialization of the memory device 16a, an initialization packet having a known data pattern is repetitively applied to the shift register 202 along with an initialization FLAG signal. As explained above, the initialization FLAG signal is a FLAG signal that is initially high for a duration that is twice the duration of the FLAG signal during normal operation. Thus, two adjacent FLAG bits, e.g., F less than 0 greater than  and F less than 1 greater than , can both be logic xe2x80x9c1xe2x80x9d. In contrast, as mentioned above, only one FLAG bit can be logic xe2x80x9c1xe2x80x9d during normal operation of the memory device 16a. The NAND gate 212 (FIGS. 3 and 4) is used to detect the initialization FLAG signal by detecting when the F less than 0 greater than  and F less than 1 greater than  FLAG bits are both logic xe2x80x9c1xe2x80x9d.
As further described in the Baker et al. application, during the initialization process, a predetermined initialization packet and a predetermined pattern of FLAG bits are repetitively shifted into the shift register 202. The packet words in the initialization packet and the FLAG bits are repetitively stored in the shift register 202 using different phases of the ICLK signal, as determined by an internal logic circuit (not shown). The bits of the packet words and the FLAG bits stored in the shift register 202 responsive to each phase of ICLK are then examined, and a determination is made of which phase of the ICLK signal was best able to capture the packet words and FLAG bits. The logic circuit then applies PHASE bits corresponding to the optimum phase of the ICLK signal to the clock generator 40. Thereafter, the clock generator 40 delays the ICLK signal relative to the CMDCLK signal so that the transition of the ICLK signal occurs at the approximate center of the capture window between t2 and t4, as illustrated in FIG. 5.
As explained above, during normal operation of the memory device 16a, the FLAG signal transitions high for one bit, as illustrated in FIG. 6. As further shown in FIG. 6, the ICLK signal has been adjusted during the initialization procedure explained above so that it transitions at the center of the FLAG bit. The high FLAG signal is clocked into the shift registered 202 thereby making the F less than 0 greater than  bit logic xe2x80x9c1.xe2x80x9d On each successive transition of the ICLK signal, the logic xe2x80x9c1xe2x80x9d is shifted through each successive stage of the shift register 202, thereby sequentially making each of the F less than 1 greater than -F less than 7 greater than  bits logic xe2x80x9c1xe2x80x9d. The logic level clocked into the shift register 202 is shown below each of the strobe arrows coincident with each transition of the ICLK signal.
The initialization FLAG signal is shown to being clocked into the shift register 202 in FIG. 7. As mentioned above, the initialization FLAG signal is twice the width of the FLAG signal occurring during normal operation. The ICLK signal is shown in FIG. 7 with its transitions occurring at the 25% and 75% portions of the doublexe2x80x94width FLAG signal. The FLAG signal as stored in the shift register 202 is thus xe2x80x9c0xe2x80x9d xe2x80x9c1xe2x80x9d xe2x80x9c1xe2x80x9d xe2x80x9c0xe2x80x9d xe2x80x9c0xe2x80x9d xe2x80x9c0xe2x80x9d, etc. so that at the second transition of ICLK, the F less than 0 greater than  and F less than 1 greater than  bits are both logic xe2x80x9c1xe2x80x9d, which is detected by the NAND gate 212.
The ICLK signal is shown in FIGS. 6 and 7 as having a phase relative to the phase of the FLAG signal that allows the ICLK signal to accurately strobe the FLAG signal. Proper phasing of the ICLK signal is insured by the initialization procedure for normal operation, as illustrated in FIG. 6. However, since the initialization FLAG signal shown in FIG. 7 is generated to signify the start of the initialization procedure, the initialization procedure has not yet occurred when the initialization FLAG signal is applied to the shift register 202. Therefore, it is possible for the phase of the ICLK signal relative to the phase of the initialization FLAG signal to be as illustrated in FIG. 8. Under these conditions, the transitions of the ICLK signal coincide with the transitions of the initialization FLAG signal so that the logic level clocked into the shift register 202 on those transitions of ICLK is indeterminate. However, the transition of ICLK occurring at the center of the initialization FLAG signal is properly registered as a logic xe2x80x9c1xe2x80x9d. The initialization FLAG signal as stored in the shift register 202 could thus be xe2x80x9c110xe2x80x9d to properly signify the start of the initialization procedure, but it could also be xe2x80x9c010xe2x80x9d to signify a normal FLAG signal or xe2x80x9c111xe2x80x9d, which signifies neither a normal FLAG signal nor an initialization FLAG signal.
The need to select the phase of the ICLK signal during the initialization procedure before the initialization FLAG signal signifying the start of the initialization procedure can be accurately detected creates an apparent inability to reliably initiate the initialization procedure. As a result, although the abovexe2x80x94described initialization procedure is capable of insuring accurate synchronization of the ICLK signal to the packet words CA0-9 and the FLAG signal, there is no apparent technique for reliably detecting the initialization FLAG signal in order to initiate the initialization procedure.
The invention is directed to a method and apparatus for detecting an initialization flag signal in a packetized DRAM. The DRAM is adapted to receive a command packet, a command clock, and either the initialization flag signal or a normal flag signal, which are applied to a flag input terminal of the DRAM. The initialization flag signal is received prior to initialization of the DRAM, and the normal flag signal is received during normal operation of the DRAM. The normal flag signal has a duration that is substantially shorter than, preferably half, the duration of the initialization flag. In accordance with the inventive method and apparatus, the flag input terminal is sampled by a suitable device, such as a plurality of latches or a shift register. The flag input terminal is sampled at a rate that is sufficiently high than a plurality of samples, preferably at least 4, are taken during the duration of the initialization flag signal. The number of contiguous samples corresponding to a predetermined logic level, such as the logic level of the flag signals, is determined. A determination is then made whether the number of these contiguous samples were taken over duration that is longer than the duration of the normal flag signal. In another aspect of the invention, a command packet and a flag signal having predetermined patterns are applied to the DRAM. The bits of the command packet are then sampled along with the flag signal, and the samples of the flag signal are compared to the samples of each bit of the command packet. If the comparison indicates that the pattern of the flag signal does not correspond to the pattern of the command packet, an error signal is generated. The inventive method and apparatus may be included in a command buffer for the packetized DRAM, and the packetized DRAM incorporating the inventive method and apparatus may be used in a computer system.